SPRS377F–SEPTEMBER2008–REVISEDJUNE2014
3.6TerminalFunctions
toidentifytheexternalsignalnames,theassociatedpin/ballnumbersalongwiththemechanicalpackagedesignator,thepintype(I,O,IO,OZ,orPWR),whetherthepin/ballhasanyinternalpullup/pulldownresistors,whetherthepin/ballisconfigurableasanIOinGPIOmode,andafunctionalpindescription.
3.6.1DeviceResetandJTAG
Table3-6.ResetandJTAGTerminalFunctions
SIGNALNAME
PINNOPTP146-152153156155150-ZKBG3L4J1J2J3H3J4J5
TYPE(1)
PULL(2)RESET
DESCRIPTION
RESETAMUTE0/RESETOUTTMSTDITDOTCKTRSTEMU[0]/GP7[15](1)(2)(3)
IO(3)IIOIII/O
IPDJTAGIPUIPUIPDIPUIPDIPU
DeviceresetinputResetoutput
JTAGtestmodeselectJTAGtestdatainputJTAGtestdataoutputJTAGtestclockJTAGtestresetEmulationSignal
I=Input,O=Output,I/O=Bidirectional,Z=Highimpedance,PWR=Supplyvoltage,GND=Ground,A=Analogsignal.
Note:Formultiplexedpinswherefunctionshavedifferenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral.
IPD=InternalPulldownresistor,IPU=InternalPullupresistorOpendrainmodeforRESETOUTfunction.
3.6.2High-FrequencyOscillatorandPLL
Table3-7.High-FrequencyOscillatorandPLLTerminalFunctions
SIGNALNAME
PINNOPTP-ZKBR12
TYPE(1)
O
PULL(2)IPU
PLLObservationClock
DESCRIPTION
EMA_CLK/OBSCLK/AHCLKR2/GP1[15]OSCINOSCOUTOSCVSSPLL0_VDDAPLL0_VSSA(1)(2)
1.2-VOSCILLATOR
143145144141142
F2F1E2D1E1
IOGND
1.2-VPLL
PWRGND
PLLanalogVDD(1.2-Vfilteredsupply)PLLanalogVSS(forfilter)OscillatorinputOscillatoroutput
Oscillatorground(forfilteronly)
I=Input,O=Output,I/O=Bidirectional,Z=Highimpedance,PWR=Supplyvoltage,GND=Ground,A=Analogsignal.
Note:Formultiplexedpinswherefunctionshavedifferenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral.
IPD=InternalPulldownresistor,IPU=InternalPullupresistor
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SPRS377F–SEPTEMBER2008–REVISEDJUNE2014
Table3-9.ExternalMemoryInterfaceA(EMIFA)TerminalFunctions(continued)
SIGNALNAME
EMA_A[12]/LCD_MCLK/GP1[12]EMA_A[11]/LCD_AC_ENB_CS/GP1[11]EMA_A[10]/LCD_VSYNC/GP1[10]EMA_A[9]/LCD_HSYNC/GP1[9]EMA_A[8]/LCD_PCLK/GP1[8]EMA_A[7]/LCD_D[0]/GP1[7]EMA_A[6]/LCD_D[1]/GP1[6]EMA_A[5]/LCD_D[2]/GP1[5]EMA_A[4]/LCD_D[3]/GP1[4]EMA_A[3]/LCD_D[6]/GP1[3]
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]EMA_A[0]/LCD_D[7]/GP1[0]
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]EMA_BA[0]/LCD_D[4]/GP1[14]EMA_CLK/OBSCLK/AHCLKR2/GP1[15]EMA_SDCKE/GP2[0]
EMA_RAS/EMA_CS[5]/GP2[2]EMA_CAS/EMA_CS[4]/GP2[1]EMA_RAS/EMA_CS[5]/GP2[2]EMA_CAS/EMA_CS[4]/GP2[1]EMA_CS[3]/AMUTE2/GP2[6]
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]EMA_CS[0]/UHPI_HAS/GP2[4]EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]PINNOPTP424127403937363534323130292625------2123-55
ZKBN11P11N8R11T11N10P10R10T10N9P9R9T9P8R8R12T12N7L16N7L16T7P7T8M13
TYPE(1)
OOOOOOOOOOOOOOOOOOOOOOOOO
PULL(2)IPUIPUIPUIPUIPUIPDIPDIPDIPDIPDIPUIPUIPDIPUIPUIPUIPUIPUIPUIPUIPUIPUIPUIPUIPU
EMIFAchipselect,GPIOMMCSD,UHPI,GPIOLCD,GPIOLCD,UHPI,GPIOLCD,GPIOMcASP2,GPIOGPIO
EMIFAclockEMIFASDRAMclockenable
EMIFASDRAMrowaddressstrobeEMIFASDRAMcolumnaddressstrobe
EMIFAbankaddressEMIFAaddressbus
LCD,GPIO
EMIFAaddressbus
MUXED
DESCRIPTION
EMIFA
SDRAM,GPIOMcASP2,GPIOUHPI,GPIO,BOOTUHPI,GPIO
EMIFASDRAMchipselect
EMIFAAsyncChipSelect
UHPI,
EMIFASDRAMwrite
MCASP0,
enable
GOPIO,BOOT
EMIFAwrite
enable/datamaskfor
UHPI,McASP,EMA_D[15:8]GPIOEMIFAwrite
enable/datamaskforEMA_D[7:0]UHPI,McASP0,GPIOUHPI,GPIO
EMIFAoutputenableEMIFAwaitinput/interrupt
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]-P12OIPU
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]-M14OIPU
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]EMA_WAIT[0]/UHPI_HRDY/GP2[10]2219
R7N6
OI
IPUIPU
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